Four MTIA Chips in Two Years: Scaling AI Experiences for Billions

Every day, billions of people on Meta’s platforms enjoy an array of AI-powered experiences ranging from personalized recommendations to AI assistants. Meanwhile, the AI models that will define the next era of computing are evolving faster than any single hardware generation can anticipate. Serving a wide range of AI models on a global scale, while maintaining the lowest possible costs, is one of the most demanding infrastructure challenges in the industry. Our response is to define the path forward — delivering flexible solutions today and improving them continuously as needs evolve.

While we remain committed to a diverse silicon portfolio and to leveraging the best solutions available — both internally and externally — the Meta Training and Inference Accelerator (MTIA), our family of homegrown AI chips developed in close partnership with Broadcom, has remained and will continue to be an important part of Meta’s AI infrastructure strategy. MTIA plays an important role in cost-effectively powering AI experiences for the billions of people who use Meta’s products.

We have published research papers at ISCA’23 and ISCA’25 detailing the first two generations of MTIA chips: MTIA 100 and MTIA 200 (formerly known as MTIA 1 and MTIA 2i). More importantly, we have deployed hundreds of thousands of MTIA chips in production, onboarded numerous internal production models, and tested MTIA with large language models (LLMs) like Llama.

Since introducing MTIA 100 and 200, we have accelerated MTIA development across four successive generations: MTIA 300, 400, 450, and 500. These new chips have either already been deployed or are scheduled for deployment in 2026 or 2027, expanding workload coverage from ranking and recommendation (R&R) inference to R&R training, general GenAI workloads, and GenAI inference with targeted optimizations.

AI models are evolving faster than traditional chip development cycles. Chip designs are based on projected workloads, but by the time the hardware reaches production — often two years later — those workloads may have shifted substantially. Rather than placing a bet and waiting for a long period of time, we deliberately take an iterative approach: Each MTIA generation builds on the last, using modular chiplets, incorporating the latest AI workload insights and hardware technologies, and deploying on a shorter cadence. This tighter loop keeps our hardware better aligned with evolving models while enabling faster adoption of new technology.

The MTIA family now includes:

• MTIA 300: Initially optimized for R&R models — the dominant Meta workload before GenAI took off — its building blocks established a strong foundation for subsequent chips optimized for GenAI models. It is in production for R&R training.
• MTIA 400: As GenAI surged, MTIA 300 evolved into MTIA 400 to better support GenAI models, while maintaining the capabilities for supporting R&R workloads. Featuring a 72-accelerator scale-up domain, MTIA 400 delivers high performance that is competitive with leading commercial products. We have finished testing MTIA 400 in our labs and are on the path to deploying it in our data centers.
• MTIA 450: Anticipating the rise in GenAI inference demand, MTIA 400 transitioned into MTIA 450, with specific optimizations for GenAI inference. Since the bandwidth of high-bandwidth memory (HBM) is the most important factor affecting GenAI inference performance, we doubled HBM bandwidth from MTIA 400 to 450, making it much higher than that of existing leading commercial products. Additionally, we introduced low-precision data types co-designed for inference workloads. MTIA 450 is scheduled for mass deployment in early 2027.
• MTIA 500: Continuing the focus on GenAI inference, MTIA 500 increased HBM bandwidth by an additional 50% compared to MTIA 450 and introduced further innovations in low-precision data types. MTIA 500 is scheduled for mass deployment in 2027.

Anticipating the rapid growth in GenAI inference demand, we evolved MTIA 400 into MTIA 450, optimizing it for GenAI inference by advancing four areas:

1. Doubling HBM bandwidth from the prior version to accelerate decode.
2. Increasing MX4 FLOPS by 75% to speed up mixture-of-experts (MoE) feed-forward network (FFN) computation.
3. Introducing hardware acceleration that makes both attention and FFN computation more efficient (e.g., by alleviating Softmax and FlashAttention bottlenecks).
4. Innovating in low-precision data types.

MTIA 450 goes beyond FP8/MX8 and delivers 6x the MX4 FLOPS of FP16/BF16, reflecting the importance of low-precision FLOPS for inference. MTIA 450 also supports mixed low-precision computation without incurring the software overhead associated with data type conversion. Finally, it introduces our custom data-type innovations that preserve model quality and boost FLOPS, with minimal impact on chip area.

In the highly competitive AI chip landscape, our MTIA strategy rests on three pillars for success:

• High-velocity iterative chip development.
• Inference‑first focus.
• Frictionless adoption by building natively on industry standards like PyTorch.

Given the rapid pace of AI innovation, we have built the capability to ship a new chip roughly every six months. This fast pace offers two advantages:

• Fast adaptation to evolving AI techniques: As new model architectures, low-precision data types, and serving techniques emerge, we can optimize our latest chips for these advancements, introduce hardware acceleration for important operators, and address bottleneck shifts among compute, memory, and I/O.
• Fast adoption of the latest hardware technologies: Examples include the latest process nodes, HBM, and packaging technologies.

We achieve high velocity through a reusable and modular design across all levels: chiplets, chassis, racks, and network infrastructure. We architect our accelerators as systems of chiplets — discrete, reusable building blocks for compute, I/O, and networking. Because each chiplet can be upgraded separately, we can implement improvements in months rather than years. Moreover, different chiplets can be manufactured at different process nodes that are most cost-effective while meeting performance and power requirements.

At the system level, MTIA 400, 450, and 500 all utilize the same chassis, rack, and network infrastructure. Therefore, each new chip generation can be dropped into the same physical footprint, accelerating the transition from silicon to production deployment. Our modular, reusable designs also minimize the resources needed to develop and deploy multiple chip generations, and the benefits of these highly optimized chips can offset the resources used for development and deployment.